1. Field of the Invention
This invention relates to the detection of errors in c he memories, and more specifically to the detection of errors in instruction processor cache memories which hold operands wherein predefined bits of the operand are designated to provide block and cache array addresses.
2. Discussion of Background Art
Cache memories are used in conjunction with the instruction processors of computers to temporarily hold portions of main memory contents which are in use, or have been used relatively recently. In the instruction processor of such computer systems, cache memories may be used to store operands. The advantage of a cache memory is that data in it can be accessed in a small fraction of the time that is required to access the main memory. Therefore, if the cache contents, such as an operand, have been used relatively recently, the operand can be obtained from the cache memory without a time-consuming reference to the main memory. Whereas main memory access time has held relatively constant at 300 to 600 nanoseconds in recent years, information can be obtained from a cache memory in as short a time period as 10 nanoseconds with current technology.
The operation of cache memories and their advantages are well known. A comprehensive overall survey of cache memories appears in the article entitle "Cache Memories" by Allen J. Smith and published by the Association for Computing Machinery (ACM) in Computing Surveys, Vol. 14, No. 3, September 1982, pp. 473-530.
Cache memories are often organized into a number of blocks each of which have a fixed set of words associated therewith. The organization of cache buffers into blocks is shown in U.S. Pat. No. 3,967,247, issued Jun. 29, 1976 to Vernon K. Anderson and Michael W. Goddard, and in U.S. Pat. No. 4,168,541, issued Sep. 18, 1979 to Clarence W. Dekarske. Both of the patents are assigned to the predecessor of the assignee of the present invention. A variation of this type of cache memory is provided by dividing each block into even word and odd word sections and by interleaving access of even and odd words alternately.
As shown in the Dekarske patent, a tag buffer may be associated with the cache memory which is also divided into a number of blocks. The tag cache holds tags which represent a portion of the memory address bits of the words which are currently held in the cache memory. When a match is achieved between a tag and the address that is supplied to the cache memory, the appropriate word is selected from the block of the cache memory that provided the matching tag.
U.S. Pat. No. 3,789,204 entitled "Self Checking Digital Storage System" which issued Jan. 29, 1974 to George Joseph Barlow discloses a system and a method for detecting faults within a self-checking digital storage system with capabilities of generating a data parity bit indicative of the data parity to be stored in the digital storage system, generating a first address parity bit indicative of the address parity where the data is to be stored, forming of a combined parity bit from the data parity and the address parity bit, storing the combined parity bit and the data in a selected location addressed by the address, accessing the combined parity bit along with the data whenever the data is read out of the digital storage system. Barlow also discloses a generating of a second address parity bit for the address utilized to effect the read out of the data and the combined parity bit, a forming of a reconstructed parity bit, and a comparing of the reconstructed parity bit with a parity bit of the data output.
The method and system of the Barlow patent, however, do not teach the implementation of a failure detection system or method for set associative cache memories which are divided into a number of blocks that are grouped into even and odd sets of words, and the memory is addressed through block and tag address bits. Further, the Barlow method will create problems for a large system at the system initialization since data in RAMs must be parity correct at all times. Therefore, the RAMs must be written at the system initialization by being scanned in or written in via a special hardware.
The present invention is implemented as a set associative manner wherein the memory is divided into a number of blocks which are subdivided into even and odd words that are grouped in a number of sets of words and the memory is addressed through block and tag address groups. An example of a prior set associative cache memory and its operation is found in U.S. Pat. No. 4,945,512 entitled "High-Speed Partitioned Set Associative Cache Memory," issued Jul. 31, 1990 to Clarence W. Dekarske et al. and assigned to the assignee of the present invention.